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M2201
2-Wires 1 Kbit (x8) Serial EEPROM
TWO WIRE SERIAL INTERFACE 100.000 ERASE/WRITE CYCLES with 100 YEARS DATA RETENTION at 55C SINGLE SUPPLY VOLTAGE: - 4.5V to 5.5V for M2201 version - 2.7V to 5.5V for M2201V version HARDWARE WRITE CONTROL 100 KBIT TRANSFER RATE BYTE WRITE PAGE WRITE (up to 4 BYTES) SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP DESCRIPTION The M2201 is a simplified 2-wire bus 1 Kbit electrically erasable programmable memory (EEPROM), organized as 128 x8 bits. It is manufactured in STMicroelectronics's Hi-Endurance Advanced CMOS technology which guarantees a data retention of 100 years at 55C. The M2201 is available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. The memory is compatible with a two wire serial interface which uses a bi-directional data bus and serial clock. Read and write operations are initiated by a START condition generated by the bus master and ended by a STOP condition. Address bits and RW bit are defined in one single byte, instead of two (or three) bytes for the standard I2C protocol.
8 1
PSDIP8 (B) 0.25mm Frame
8 1
SO8 (M) 150mil Width
8 1
TSSOP8 (DW) 169 mil width
Figure 1. Logic Diagram
VCC
SCL WC M2201
SDA
Table 1. Signal Names
SDA SCL WC VCC VSS Serial Data Input/Output Serial Clock Write Control Supply Voltage Ground
VSS
AI01321
July 1999
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M2201
Figure 2A. DIP Pin Connections Figure 2B. SO and TSSOP Pin Connections
M2201 NC NC NC VSS 1 2 3 4 8 7 6 5
AI01322
M2201
VCC WC SCL SDA
NC NC NC VSS
1 2 3 4
8 7 6 5
AI01323
VCC WC SCL SDA
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering (SO8 package) (PSDIP8 package) (TSSOP8 package) 40 sec 10 sec t.b.c. Value -40 to 85 -65 to 150 215 260 t.b.c. -0.6 to 6.5 -0.6 to 6.5 -0.3 to 6.5
(2)
Unit C C C V V V V V
VO VI VCC VESD
Output Voltage Input Voltage Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3)
4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 ). 3. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont'd) When writing data to the memory, it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal.
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M2201
SIGNAL DESCRIPTIONS Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3). Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3). Write Control (WC). An hardware Write Control feature (WC) is offered on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or disable (WC = VIL) the internal write protection. When unconnected, the WC input is internally read as VIL (WC is disabled). DEVICE OPERATION The device that controls the data transfer is known as the master. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The M2201 is always a slave device in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the M2201 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the M2201 and the bus master. A STOP condition at the end of a Read command forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the M2201 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS)
20 VCC 16 RL RL
RL max (k)
12 MASTER 8
SDA SCL CBUS
CBUS 4 VCC = 5V 0 100 200 CBUS (pF) 300 400
AI01100
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M2201
Table 3. Input Parameters (TA = 25 C, f = 100 kHz )
Symbol CIN CIN ZWCL (1) ZWCH (1) tLP (1) Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Low-pass filter input time constant (SDA and SCL) VIN 0.3 VCC VIN 0.7 VCC 5 500 100 Test Condition Min Max 8 6 20 Unit pF pF k k ns
Note: 1. The results come from simulation, actual results may vary. These figures are not guaranteed.
Table 4. DC Characteristics (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5V to 5.5V or 2.7V to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current (M2201) Supply Current (M2201V) Supply Current (Standby) (M2201) Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V; fC = 100kHz (Rise/Fall time < 30ns) VCC = 2.7V; fC = 100kHz VIN = VSS or VCC, VCC = 5V VIN = VSS or VCC, VCC = 5V, fC = 100kHz VIN = VSS or VCC, VCC = 2.7V VIN = VSS or VCC, VCC = 2.7V; fC = 100kHz -0.3 0.7 VCC -0.3 VCC - 0.5 IOL = 3mA, VCC = 5V IOL = 2mA, VCC = 2.7V Min Max 2 2 2 1 100 300 5 50 0.3 VCC VCC + 1 0.5 VCC + 1 0.4 0.4 Unit A A mA mA A A A A V V V V V V
ICC
ICC1
ICC2
Supply Current (Standby) (M2201V)
VIL VIH VIL VIH VOL
Input Low Voltage (SCL, SDA) Input High Voltage (SCL, SDA) Input Low Voltage (WC) Input High Voltage (WC) Output Low Voltage (M2201) Output Low Voltage (M2201V)
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M2201
Table 5. AC Characteristics (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5V to 5.5V or 2.7V to 5.5V)
Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL1 tCHDX (1) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV
(2)
Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time Input Rise Time Input Fall Time
Parameter
Min
Max 1 300 1 300
Unit s ns s ns s s s s s ns s s
Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time
4.7 4 4 0 4.7 250 4.7 4.7 0.3 300 100 10 3.5
s ns kHz ms
tCLQX fC tW
Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions.
Table 6. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 50ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.7VCC 0.3VCC
AI00825
0.2VCC
Memory Addressing. To start communication between the bus master and the slave M2201, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the 7th bit byte-address and a READ or WRITE bit. This 8th bit is set to '1' for read and '0' for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time. Write Operations Following a START condition the master sends the byte address with the RW bit reset to '0'. The memory acknowledges this and waits for a data byte. Any write command with WC = 1 (during a period of time from the START condition until the end of the Byte Address) will not modify data and will NOT be acknowledged on data bytes, as in Figure 8.
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M2201
Figure 5. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE
tCLCH
tDXCX
tCHDH
tDHDL STOP & BUS FREE
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795B
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M2201
Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. Page Write. The Page Write mode allows up to 4 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the 5 most significant memory address bits (A6-A2) are the same. The master sends from one up to four bytes of data, which are each acknowledged by the memory. After each byte is transfered, the internal byte address counter (2 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'roll-over' which could result in data being overwritten. It must be noticed that, for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be re-
Figure 6. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
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M2201
- Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1).
DEVICE OPERATION (cont'd) duced by an ACK polling sequence issued by the master. The sequence is as follows: - Initial condition: a Write is in progress (see Figure 7). - Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction).
Figure 7. Write Cycle Polling using ACK
WRITE Cycle in Progress
START Condition Byte Address with RW = 0
NO
ACK Returned YES
NO
Next Operation is WRITE
YES
ReSTART
Send DATA BYTE
STOP
STOP
AI01049
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M2201
Read Operation Byte Read. The master sends a START condition followed by seven bits of address and the RW bit (set to '1'). The M2201 acknowledges it and outputs the corresponding data byte. The read operation is terminated by a STOP condition issued by the master (instead of the ACK bit). Sequential Read. The master sends a START condition followed by seven bits of address and the RW bit (set to '1'). The M2201 acknowledges it and outputs the corresponding data byte. The master does acknowledge this byte and reads the next data byte (at address + 1). The read operation is terminated by a STOP condition issued by the master (instead of the ACK bit). The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will 'rollover to address '00' and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the M2201 waits for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the M2201 terminates the data transfer and switches to a standby state.
Figure 8. Write Modes Sequences with Write Control = 1 (M2201 and M2201V)
WC ACK BYTE WRITE BYTE ADDR NO ACK DATA IN
START
R/W = 0
WC ACK PAGE WRITE BYTE ADDR NO ACK DATA IN 1 NO ACK NO ACK
STOP
DATA IN 4
START
R/W = 0
AI01324
STOP
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M2201
Figure 9. Write Modes Sequences (M2201 and M2201V)
ACK BYTE WRITE Byte-Address Data-In ACK
START
R/W=0 ACK
ACK Data-In1 Data-In 2
STOP
ACK Data-In 3
PAGE WRITE
Byte-Address
START
R/W=0 ACK Data-In N ACK
STOP
AI03128
Figure 10. Read Modes Sequences
ACK BYTE READ BYTE ADDR
NO ACK DATA OUT
START
R/W = 1
ACK SEQUENTIAL READ BYTE ADDR
ACK
STOP
ACK
NO ACK
DATA OUT 1
DATA OUT N
START
R/W = 1
10/15
STOP
AI01325
M2201
ORDERING INFORMATION SCHEME
Example:
M2201
V
M
1
TR
Operating Voltage blank 4.5V to 5.5V V 2.7V to 5.5V M DW B
Package PSDIP8 0.25mm Frame SO8 150mil Width TSSOP8 169mil width
Temperature Range 1 6 0 to 70 C -40 to 85 C TR
Option Tape & Reel Packing
Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information please contact the STMicroelectronics Sales Office nearest to you.
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M2201
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb Typ A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 mm Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Drawing is not to scale.
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M2201
SO8 - 8 lead Plastic Small Outline, 150 mils body width
Symb Typ A A1 B C D E e H h L N CP 1.27 mm Min 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Drawing is not to scale.
13/15
M2201
TSSOP8 - 8 lead Plastic Thin Shrink Small Outline, 169 mils body width
mm Typ A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 - 0.50 0 8 0.08 Min Max 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 - 0.020 0 8 0.003 Typ inches Min Max 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 - 0.028 8
Symb
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
Drawing is not to scale.
B
e TSSOP
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M2201
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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